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ics for communications octal transceiver for u pn interfaces octat-p peb 2096 version 2.1 data sheet 04.99 ds 2
? for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 2096 revision history: current version: 04.99 previous releases: data sheet 01.96 page (in previous version) page (in current version) subjects (major changes since last revision) 9 9 pin configuration (correction pin 17 and 18) - 19 data rate on iom-2 interface: up to 8192 kbit/s 21 22 revision number for v2.1 40 42 correction of state diagram 45 46 correction of activation and deactivation example - 49 delay measurement 53 56 correction of ac characteristics 60 63 new figure on upn frame relation to fsc edition 04.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i. gr. 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag.
peb 2096 table of contents page data sheet iii 04.99 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2.1 general principle of the u pn interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2.2 iom ? -2 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3 jtag boundary scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.3.1 boundary scan test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3.2 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3 individual functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.1 transceiver, analog connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.2 transmit pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.3 receive pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.4 receive signal oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.5 activation / deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.6 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 clocking, reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3 tristate capability on iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.4 push C pull sensing on pin du . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.5 transmit delay on u pn interface in respect to iom ? -2 interface . . . . . . . . 3-2 3.6 upn multiframe synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.6.1 synchronization with a short fsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.6.2 synchronization using ssync (for dect) . . . . . . . . . . . . . . . . . . . . . . 3-4 3.7 d-channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.8 iom ? -2 interface monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.9 command / indicate channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.10 activation and deactivation, state machine . . . . . . . . . . . . . . . . . . . . . . 3-13 3.10.1 states description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.10.2 info structure on the u pn interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.10.3 example of activation and deactivation . . . . . . . . . . . . . . . . . . . . . . . 3-18 4 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 identification register C (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 general configuration register C (write) . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 bit error register C (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
peb 2096 table of contents page data sheet iv 04.99 4.4 test registers C (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.5 line delay measurement of the u pn interface . . . . . . . . . . . . . . . . . . . . . . 4-3 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.5 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.6 timing of the iom ? interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.7 boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.8 u pn frame relation to fsc in transmit direction . . . . . . . . . . . . . . . . . . 5-12 5.9 transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
peb 2096 overview data sheet 1-1 04.99 1 overview the new infineon technologies generation of highly integrated isdn circuits enables design engineers to decrease board size and thus pbx size and its production costs. figure 1-1 shows an example of a pbx for 16 isdn and 16 analog subscribers with 4 trunk lines realized with a few highly integrated chips of the new infineon technologies family of pbx and line card ics: doc, sicofi-4, octat-p and quat-s. ? figure 1-1 application example pbx for 32 subscribers with 4 trunk lines using one doc doc , dsp oriented pbx controller, peb 20560. the doc integrates many different functional blocks on a single chip for building small pbxs or pbx line cards: two elics, its10068 peb 2465 slic t/r u p s t r iom -2 doc peb 20560 pcm highways memory data and program signaling m p interface memory power supply m p slic slic slic sicofi r -4 v.24 up to 56 kw dsp octat r -p peb 2096 quat peb 2084 -s r quat peb 2084 -s r 0 15 0 7 0 7 0 3 office central
peb 2096 overview data sheet 1-2 04.99 enhanced line card controller (peb 20550), one sidec, 4-channel signaling controller (lapd), multiple iom-2 and pcm interfaces, one up to 40 mips dsp with on-chip emulation and a mailbox, one pcm-dsp interface for fast dsp access, one uart, interrupt controller, the doc is a cmos device offered in a p-mqfp-160 package. quat ? -s , quadruple transceiver for s/t interfaces, peb 2084, implements 4 four-wire s/t interfaces to link voice/data digital terminals to pbx subscriber lines and pbx trunk lines to the public isdn. it can handle up to four s/t interfaces simultaneously in accordance with ccitt i.430, etsi 300.012, and ansi t1.605 standards. the quat-s is a cmos device offered in a p-mqfp-44 package. octat ? -p , octal transceiver for u pn interfaces, peb 2096, implements the two-wire u pn interface used to link voice/data digital terminals to pbx subscriber lines. the octat-p is an optimized device for lt applications and can handle up to eight u pn interfaces simultaneously. it handles the u pn interfaces in accordance with the u p0 interface specification except for the reduced loop length. the octat-p is a cmos device offered in a p-mqfp-44 package. sicofi ? -4, programmable signaling and codec filter with 4 channels, peb 2465, implements 4 t/r (a/b) interfaces to link analog voice terminals to pbx subscriber lines and analog pbx trunk lines to public switches. an integrated digital signal processor handles all the algorithms necessary e.g. transhybrid-loss adaption, gain, frequency response, impedance matching. the iom-2 interface handles digital voice transmission, sicofi-4 feature control and transparent access to the sicofi-4 command and indication pins. to program the filters, precalculated sets of coefficients are downloaded from the system to the on-chip coefficient ram. thus it is possible to use the same line card in different countries. the sicofi-4 is a cmos device offered in p-mqfp-64 package. isdn-oriented modular interface (iom ? -2) the group of four, alcatel, siemens, plessey and italtel systems houses, originally defined a general circuit interface (gci) with the aim of specifying a comprehensive interface which would allow various telecommunication devices to communicate in an efficient manner. the iom-2 interface is a four-wire interface. it became a standard interface for interchip communication in isdn applications. all above ics are compatible and operate from a single 5 v power supply.
p-mqfp-44 data sheet 1-3 04.99 octal transceiver for u pn interfaces octat-p peb 2096 version 2.1 cmos type package peb 2096 p-mqfp-44 1.1 features ? eight full duplex 2b+d u pn interface transceivers, each equipped with the following functions: Cconversion from/to binary to/from pseudo-ternary code Creceive timing recovery Cactivation/deactivation procedures, triggered by primitives received over the iom interface or by info received from the line (e.g. detection of info 1) Cline delay measurement Cexecution of test loops Canalog line transceiver for up to 16 db line attenuation Cu pn interface functions compatible to peb 2095, ibc, and peb 20950, isac-p (except for looplength) Cu pn interface fully compatible to psb 2196, isac-p te, psb 2197, smartlink-p, scout ? iom-2 interface ? support for jtag boundary scan test ?1 m cmos technology with low power consumption ? p-mqfp-44 package note: u pn refers to a version of the standard interface u p0 (according to zvei standard) with a reduced loop length (up to 1.3 km).
peb 2096 overview data sheet 1-4 04.99 1.2 logic symbol ? figure 1-2 logic symbol
peb 2096 overview data sheet 1-5 04.99 1.3 pin configuration (top view) ? figure 1-3 pin configuration itp04456 li7b li7a li6b li6a li5b li5a li4b li4a li3b li3a li2b li2a li1b li1a li0b li0a v dd v dd v ss v dd v ss v dd v ss v dd v ss v ss v dd v ss 44 1 12 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 tdo fsc dcl tdi dd tck du tms ids ssync rst mode clk1 xtal1 clk2 xtal2 p-mqfp-44
peb 2096 overview data sheet 1-6 04.99 1.4 pin definitions and functions pin no. symbol input (i) output (o) function 6, 12, 22, 28, 34, 44 3, 9, 19, 25, 31, 37 v dd v ss i i + 5 v power supply reference ground 33, 32 30, 29 27, 26 24, 23 1, 2 4, 5 7, 8 10, 11 li0a,b li1a,b li2a,b li3a,b li4a,b li5a,b li6a,b li7a,b i/o i/o i/o i/o i/o i/o i/o i/o u pn line interfaces a,b no. 0: differential input / output no. 1: differential input / output no. 2: differential input / output no. 3: differential input / output no. 4: differential input / output no. 5: differential input / output no. 6: differential input / output no. 7: differential input / output 43 42 41 40 39 fsc dcl dd du ids i i i o i iom ? -2 interface frame synchronization clock: 8 khz data clock data downstream (data input) data upstream (data output) interface data rate select (static pin-strapped): 0: double dcl (normal iom interface) 1: single dcl 16 15 14 13 tms tck tdi tdo i i i o jtag boundary scan interface test mode select, internal pull-up resistor test clock test data input, internal pull-up resistor test data output 20 21 xtal1 xtal2 i o oscillator or 15.36 mhz clock input oscillator output 36 clk1 o clock output 15.36 mhz (i.e. to drive other octat-p) 35 clk2 o clock output 7.68 mhz (i.e. to drive isac-s or quat-s) 38 rst i reset, active high
peb 2096 overview data sheet 1-7 04.99 18 ssync i superframe synchronization 17 mode i this pin selects the initial values of the general configuration register and in the configuration register for u pn line interfaces as described in chapter 4.2 and chapter 4.4 . it also enables push-pull sensing on pin du as described in chapter 3.4 . 1.4 pin definitions and functions (contd) pin no. symbol input (i) output (o) function
peb 2096 overview data sheet 1-8 04.99 1.5 block diagram ? figure 1-4 block diagram
peb 2096 functional description data sheet 2-1 04.99 2 functional description the peb 2096, octat-p, performs the layer-1 functions of the isdn basic access for eight u pn interfaces at the lt side of the pbx. 2.1 device architecture the octat-p contains the following functional blocks: refer to figure 1-4 ? eight line transceivers for the u pn interfaces ? one iom-2 interface ? frame structure converter between the iom-2 interface and the u pn interfaces ? jtag boundary scan interface ? clocking, reset and initialization block 2.2 interfaces 2.2.1 general principle of the u pn interface a frame transmitted by the exchange (lt) is received by the terminal equipment (te) after a given propagation delay ( t d ). refer to figure 2-1 . the terminal equipment waits a minimum guard time ( t g =5.2 m s) while the line clears. it then transmits a frame to the exchange. the exchange begins a transmission every 250 m s (known as the burst repetition period). however, the time between the reception of a frame from the te and the beginning of transmission of the next frame by the lt must be greater than the minimum guard time. communication between an lt and a pt (private termination) follows exactly the same procedure. note that the guard time in te is always defined with respect to the m-bit.
peb 2096 functional description data sheet 2-2 04.99 ? figure 2-1 u p0 interface frame structure (= u pn ) within a burst, the data rate is 384 kbit/s. the 38-bit frame structure is as shown in figure 2-1 . the framing bit (lf) is always logical 1. the frame also contains the user channels (2b + d). it can readily be seen that in the 250 m s burst repetition period, 4 d bits, 16 b1 bits and 16 b2 bits are transferred in each direction. this results in an effective full duplex data rate of 16 kbit/s for the d channel and 64 kbit/s for each b channel. the final bit of the frame is called the m bit. its data rate is 4 kbit/s. four successive m bits, from four successive u frames, constitute a superframe. three signals are carried in this superframe. every fourth m bit is a code violation (cv) and is used for superframe synchronization. this can be regarded as the first bit of the superframe. from this reference (cv = bit 1), bit 3 of the superframe is the service channel bit s. this itd00823 lf b1 b2 8 1 8 d 4 8 8 b2 b1 m dc 2) 1 #bits 1 cv t s t cv t s t cv 1) 2) m channel superframe cv = code violation: for superframe synchronization t = transparent channel (2 kbit/s) s = service channel (1 kbit/s) dc balancing bit, only sent after a code violation in the m-bit position and in special configurations. timings: = burst repetition period = 250 = ine delay = 20.8 = guard time = 5.2 t r d t t g m s s m m s maximum minimum g t t d r t d t 99 m s lf-framing bit lt te/pt )
peb 2096 functional description data sheet 2-3 04.99 s-channel bit is transmitted once in each direction in every fourth burst repetition period. hence the duplex s channel has a data rate of 1 kbit/s. it conveys test loop control information from the lt to the te/pt and reports of transmission errors from the te/pt to the lt. bit 2 and bit 4 of the superframe are the t bits. this 2 kbit/s channel is accessible via the c/i channel and may be used to carry the available/blocked information sent by the d-channel arbiter of the peb 20550, elic. it is allowed to add a dc balancing bit to the burst, in order to decrease dc offset voltage on the line after transmission of a cv in the m-bit position. the octat-p transmits this dc balancing bit when transmitting info 4 and when line characteristics indicate potential decrease in performance. the octat-p scrambles b-channel data on the u pn interface in order to ensure that the downstream receiver (e.g. isac-p te) gets enough pulses for a reliable clock extraction (flat continuous power density spectrum is provided) and no periodic patterns appear on the line. the scrambling is in accordance with ccitt v.27. the coding technique used on the u interface is a half-bauded ami code (with a 50 % pulse width). a logical 0 corresponds to a neutral level, logical 1s are coded as alternate positive and negative pulses. code violation (cv) is caused by two successive pulses with the same polarity. see figure 2-2 . the ami coding includes always the data bits going on the u pn interface in one direction. thus there is a separate ami coding unit for data downstream and one for data upstream. ? figure 2-2 ami coding on the u pn interface
peb 2096 functional description data sheet 2-4 04.99 2.2.2 iom ? -2 system interface the peb 2096, octat-p, is equipped with a digital isdn oriented modular (iom-2) interface, for communication with upper layer functions, such as idec (peb 2075), epic (peb 2055) and elic (peb 20550). epic and elic represent the first switching stage towards the exchange system. refer to figure 2-3 . ? figure 2-3 system integration, iom ? interface the iom interface is a four-wire serial interface with a data clock (dcl), an 8 khz frame synchronization clock (fsc), and one data line per direction: data downstream (dd) and data upstream (du). one iom-2 frame consists of up to 8 iom channels (subframes) ( figure 2-4 ). its05394 peb 2096 octat -p psb 2165 elic control c/i iom peb 20550 psb 2196 dd dcl fsc du te 0 du fsc dcl dd c/i port no. 0 pcm port no. 0 memory pcm no. 1 no. 3 no. 2 b2 b1 8 mon 4 1 mr mx 1 2 d c/i 8x m p lt terminals u pn 0 7 te 7 du fsc dcl dd pn u r r r r arcofi -sp m c r iom -2 iom -2 r m c r isac -p te psb 2165 arcofi -sp r psb 2196 isac -p te r iom -2 line card mode = r iom r iom -2 r psb 21393 scout-px
peb 2096 functional description data sheet 2-5 04.99 ? figure 2-4 multiplexed frame structure of the iom ? -2 interface in lt-mode with 2.048 mbit/s data rate each iom channel consists of a total of 32 bits, or four octets: b1 + b2 + d (18 bits) plus 14 overhead bits for monitor and control information (activation/deactivation of osi layer-1 and maintenance functions). the isdn user data rate is 144 kbit/s (b1 + b2 + d). the data is transmitted transparently synchronous and in phase in both directions over the iom interface using time division multiplexing within the 125 m s iom-2 interface frame. nominal bit rate of data (dd and du): 256 kbit/s 4096 kbit/s nominal frequency of dcl: 512 khz 8192 khz nominal frequency of fsc: 8 khz note: the bit rate must be a multiple of 256 kbit/s. itd04319 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 b1 b2 monitor d c/i mm rx fsc dcl du dd ch0 ch0 s 125 r iom r iom
peb 2096 functional description data sheet 2-6 04.99 in order to allow the use of the eight channels also with a maximum clock rate of 2,048 khz provided by the system, the octat-p can also run the iom interface with only half the nominal dcl clock rate, i.e. 2,048 khz for 2,048 kbit/s (input pin ids = 1). the octat-p requires three iom frames to synchronize to the dcl frequency. a corrupted iom frame caused by different amount of dcl pulses within two consecutive iom frames (e.g. caused by spikes on dcl or fsc) resets internally all registers and the activation and deactivation state machine, figure 3-8 . the allocation between u pn line interfaces and the iom-2 interface channels is according to their numbers, i.e. li0a,b is allocated to iom channel 0, li1 to channel 1, and so on. for details refer to figure 2-1 and figure 2-2 and to the chapter 5.8 and the iom interface specification, rev. 2. monitor channel the monitor channel is used to convey messages (e.g. when a bit error occurs on u pn ) or for access to internal registers: identification register, general configuration register, bit error register, configuration register for u pn and test registers. the peb 2096, octat-p, has implemented the monitor channel protocol according to the iom interface specification, rev. 2, in the first of the eight iom channels allocated to the eight u pn interfaces. refer also to the chapter 3.8 . c/i-channel the c/i-channel is used for communication between the peb 2096, octat-p, and a processor via a layer-2 device, to control and monitor layer-1 functions. the octat-p has 8 iom-2 channels and thus 8 c/i-channels; one for each transceiver. the codes originating from layer-2 devices are called commands, those from the peb 2096, octat-p, are called indications. for a list of the c/i (command/indication) codes and their use, refer to the chapter 3.9 .
peb 2096 functional description data sheet 2-7 04.99 data rates on iom-2 interface the octat-p supports the following types of iom-2 interfaces: ? notes: 1. one octat-p requires 8 complete iom channels. 2. additional delayed fscs are needed in modes 4 and 8 for connecting several octats to the iom bus. 2.2.3 jtag boundary scan test interface the octat-p provides fully ieee standard 1149.1 compatible boundary scan support to allow cost effective board testing. it consists of: ? complete boundary scan test ? test access port controller (tap) ? four dedicated pins (tck, tms, tdi, tdo) ? one 32-bit idcode register ? specific functions for lina,b table 1 mode of iom-2 interface 2 4 8 nominal bit rate of data (dd and du) 2048 kbit/s 4096 kbit/s 8192 kbit/s nominal frequency of dcl (2 x data rate) 4096 khz 8192 khz not supported selectable frequency of dcl (1 x data rate) 2048 khz 4096 khz 8192 khz nominal frequency of fsc 8 khz 8 khz 8 khz number of iom channels per one iom-2 frame 81632 number of time slots per one iom-2 frame 32 64 128 number of octat-p on one iom-2 interface 124
peb 2096 functional description data sheet 2-8 04.99 2.2.3.1 boundary scan test the following octat-p pins are included in the boundary scan: clk2, clk1, rst, ids, du, dd, dcl, fsc, mode, ssync , xtal1. three additional user specific instruction codes control the transmission of continuous pulses at the line interface lina,b. depending on the pin functionality one or two boundary scan cells are provided. when the tap controller is in the appropriate mode data is shifted into/out of the boundary scan via the pins tdi/tdo using a 6.25 mhz clock on pin tck. the octat-p pins are included in the following sequence in the boundary scan: pin type number of boundary scan cells usage input 1 input output 2 output, enable boundary scan boundary scan number tdi CC> pin number pin name type number of scan cells 135clk2o2 236clk1o2 338rsti1 439idsi1 540duo2 641ddi1 7 42 dcl i 1 843fsci1 917modei1 10 18 ssync i1 11 20 xtal1 i 1
peb 2096 functional description data sheet 2-9 04.99 2.2.3.2 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee st. 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the tap controller supports 8 instructions: ? 5 instructions following the standard definition and ? 3 user specific instructions. extest is used to examine the board interconnections. when the tap controller is in the state update dr, all output pins are updated with the falling edge of tck. when it has entered state capture dr the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state update dr, all inputs are updated internally with the falling edge of tck. when it has entered state capture dr the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. note: 0011 (idcode) is the default value of the instruction register. sample/preload provides a snap-shot of the pin level during normal operation or is used to preload (tdi) / shift out (tdo) the boundary scan with a test vector. both activities are transparent to the system functionality. note: the input pin xtal1 should not be evaluated. the input frequency (15.36 mhz) is not synchronous to tck (6.25 mhz) which causes unpredictable snap-shots on the pin xtal1. code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 idcode reading id code register 11xx bypass bypass operation 1001 user specific continuous pulses on lina and linb 1010 user specific continuous pulses on lina 1011 user specific continuous pulses on linb
peb 2096 functional description data sheet 2-10 04.99 idcode the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacture code (11 bits). the lsb is fixed to 1. code for the version 2.1 is 0011. version no. 0000 = v1.1 0001 = v1.2 0010 = v1.3 0011 = v2.1 note: in the state test logic reset the code 0011 is loaded into the instruction code register. bypass , a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacture code output 00xx 0000 0000 0001 0100 0000 1000 001 1 --> tdo
peb 2096 functional description data sheet 2-11 04.99 user specific instructions three different user specific pulse types are selectable, figure 2-5 . an oscillator with a 15.36 mhz clock or an external clock is necessary for 192 khz test pulse generation; according to the instruction code 9 h . ? figure 2-5 test pulse wave forms
peb 2096 functional description data sheet 2-12 04.99 2.3 individual functions 2.3.1 transceiver, analog connections the receiver input stages consist of an amplifier/equalizer, followed by a peak detector adaptive controlling the thresholds of the comparators and a digital oversampling unit. ? figure 2-6 transceiver functional blocks external to the line interface pins lina,b are connected: a transformer, external resistors and two capacitors (100 nf and 0.33 m f). voltage overload protection is achieved by adding clamping diodes. depending on the transformer ratio employed (2:1 or 1.25:1), the resistor values have to be chosen and the resistors have to be connected accordingly: figure 2-7 depicts the analog connections for a transformer with the ratio 2:1 and figure 2-8 depicts the analog connections for a transformer with the ratio 1.25:1.
peb 2096 functional description data sheet 2-13 04.99 ? figure 2-7 transceiver with a 2:1 transformer ? figure 2-8 transceiver with a 1.25:1 transformer
peb 2096 functional description data sheet 2-14 04.99 the peb 2096, octat-p, covers the electrical requirements of the u pn interface for loop lengths depending on the used transformer and the cable quality: a) if the equalizer is enabled (equdis in configuration register for u pn line interface is set to low) b) if the equalizer is disabled (equdis in configuration register for u pn line interface is set to high) concerning the 1.25:1 transformer, the maximum line attenuation is decreased by 3 db. note: the actual values of the external resistors depend on the selected transformer. the resistor values in figure 2-7 and figure 2-8 are optimal for an ideal transformer ( r cu = 0). 2.3.2 transmit pll the transmit pll (xpll) synchronizes a 768 khz transmit clock derived from the oscillator clock to fsc (8 khz). when the oscillator clock is synchronous to fsc (fixed divider ratio of 1920 from 15.36 mhz clock) the xpll will not perform any tracking after having locked the phase, i.e. the input jitter on clocks xtal and fsc will not be increased. alternatively, when a free running oscillator is used, xpll tracking increases fsc jitter by 32.5 ns (half oscillator period). 2.3.3 receive pll the receive pll (rpll) recovers bit timing from a comparator output signal. the comparator has a threshold of 90 % with respect to the signal stored by the peak detector. the rpll performs pll tracking after detecting phase shifts of the same polarity in four pulses. a phase adjustment is done by adding or substracting 65 ns (one oscillator period) to or from the 384 khz receive clock. transformer cable loop length 2:1 j-y (st) y 2 2 0.6 up to 1 km awg 26 up to 1.3 km transformer cable loop length 2:1 j-y (st) y 2 2 0.6 up to 0.8 km awg 26 up to 1.3 km
peb 2096 functional description data sheet 2-15 04.99 2.3.4 receive signal oversampling in order to additionally reduce the bit error rate in severe conditions, the octat-p performs oversampling of the received signal and uses majority decision logic. as illustrated in figure 2-9 , each received bit is sampled 6 times at 15.36 mhz clock intervals inside the estimated bit window. the samples obtained are compared against a threshold of 50 % with respect to the signal stored by the peak detector. if at least 4 samples have an amplitude exceeding the 50 % threshold, a logical 1 is considered to be detected; otherwise a logical 0 (no signal) is considered to be detected ?. figure 2-9 u pn receive signal oversampling
peb 2096 functional description data sheet 2-16 04.99 2.3.5 activation / deactivation an incorporated finite state machine controls the activation and deactivation procedures and communicates with the layer-2 unit via the iom-2 c/i channel. each of the eight c/ i channels is allocated to its corresponding line interface. 2.3.6 diagnostic functions loop 2 is activated over the iom interface with activate request loop 2 (ar2). the loop will be closed in the te after detection of the associated bit in the u pn maintenance bit (s-bit). loop 1 is activated over the iom interface with activate request loop 1 (arl). no u pn line is required. info 4 is looped back to the receiver and also sent to the u pn interface. when the receiver is synchronized, the message ai is sent in the c/i channel.
peb 2096 operational description data sheet 3-1 04.99 3 operational description 3.1 general all procedures required for data transmission over the u pn interface are implemented. these comprise the u pn interface frame and multiframe synchronization, activation/ deactivation procedure, and timing requirements such as bit rate and jitter. the internal finite state machine of the peb 2096, octat-p, controls the activation/ deactivation procedures, switching of loops and transmission of special pulse patterns. such actions can be initiated by signals on the u pn transmission line (infos) or by control (c/i) codes sent over the iom interface. refer to figure 3-8. the exchange of control information in the c/i channel is state oriented. this means that a code in the c/i channel is repeated in every iom frame until a change is necessary. a new code must be found in two consecutive iom frames to be considered valid (double last look criterion). the monitor channel is used to convey message oriented information. this means that an information in the monitor channel is transferred once, and the receiver stores that message. in order to ensure safe data transfer, a handshake procedure between monitor channel transmitter and receiver is necessary. an example show figure 3-6 and figure 3-7 . for details refer to the iom-2 interface specification, rev. 2. 3.2 clocking, reset and initialization at power up, a reset pulse (rst) should be applied to force the line interfaces of the peb 2096, octat-p, to the state reset. no clocks are required during that procedure. the pin ssync must be set to v dd if not used. after that the line interfaces of the peb 2096, octat-p, may be operated according to the state diagram ( figure 3-8 ), each controlled via the corresponding c/i channel. 3.3 tristate capability on iom-2 interface push-pull configuration is possible also in the modes > 2.048 mbit/s (> 8 iom channels). in iom channels, which are not used by the octat-p, the data upstream direction (du) line is in high impedance state (tristate) 3.4 push C pull sensing on pin du the octat-p supports configurations where multiple ics are connected to the iom-2 interface. if the mode pin is connected to v dd the octat-p senses after reset whether an external pull-up resistor is connected to pin du or not. if no resistor is detected the pin du is changed to push-pull. if a resistor is detected the pin du is changed to open
peb 2096 operational description data sheet 3-2 04.99 drain. the sensing is done within 2 consecutive iom frames at bit position 15 (last bit of b2 channel). the pin du is always push-pull if the mode pin is connected to v ss . 3.5 transmit delay on u pn interface in respect to iom ? -2 interface the octat-p causes delays of b- and on d-channels with respect to the iom channel number. figure 3-1 shows this delay at a data rate of 2.048 mbit/s. ?. figure 3-1 transmit delay of b- and d-channels
peb 2096 operational description data sheet 3-3 04.99 3.6 u pn multiframe synchronization there are two possibilities how to synchronize the u pn multiframe: with a short fsc or with ssync . 3.6.1 synchronization with a short fsc the short fsc pulse has a width of one dcl clock (in normal use the fsc is at least 2 dcl wide). the ssync input must be set to 1. the period of the short fsc pulses must be a multiple of 1 ms. the u pn frame with a code violation in the m bit starts in the iom channel 0 which follows the short fsc pulse. refer to figure 3-2 . ? figure 3-2 synchronization with a short fsc
peb 2096 operational description data sheet 3-4 04.99 3.6.2 synchronization using ssync (for dect) a zero pulse on the ssync input forces the octat-p to start a multiframe with a code violation in the next m-bit. refer to figure 3-3 . ? figure 3-3 synchronization with ssync while using ssync for u pn multiframe synchronization the short fsc signal is not allowed. if the bit synen is set (configuration register, bit 7) the zero pulse on ssync forces the octat-p also to set the t bit to 1 in the next u pn frame. if not used the ssync input must be connected to v dd . note: before using ssync if the bit synen is set, the t-bit must be set to 0 by the c/ i command ai. n = number of u pn frames.
peb 2096 operational description data sheet 3-5 04.99 3.7 d-channel handling decentralized d-channel processing can be realized by the use of only one multiplexed hdlc-controller, which is integrated with a d-channel arbiter in the elic, peb 20550. typically the d-channel load has a very bursty characteristic. taking this into account, the elic provides the capability to multiplex one hdlc-controller among several subscribers. this feature results in a drastical reduction of hardware requirements while maintaining all benefits of hdlc based signaling ( figure 3-4 ). a d-channel arbiter is used to assign the receive and transmit hdlc-channels independently to the subscriber terminals. in downstream direction the arbiter links the transmit channel to one or more (broadcast) programmable iom-2 d-channels (ports). in upstream direction the arbiter assigns the hdlc-receive channel to a requesting subscriber and indicates to all other subscribers that their d-channels are blocked, using a control channel. this configuration supports full duplex layer-2 protocols with bus capability e.g. lapd or proprietary implementations. consequently no polling overhead is necessary providing the full 16-kbit/s bandwidth of the d-channel for data exchange. ? figure 3-4 d-channel handling with only one multiplexed hdlc-controller (sacco-a) its05808 epic r d channel controlling arbiter sacco ch-a sacco ch-b elic r p d channel highway b channels highway signaling pcm interface iom -2 r
peb 2096 operational description data sheet 3-6 04.99 the control channel is unidirectional and forwards the status information of the corresponding d-channel (blocked or available) towards the subscriber terminal. different existing channel structures are used to implement the control channel between the hdlc-controllers on the line card and in the subscriber terminal. control channel implementation on the u pn -interface on u pn -line card, the control channel is integrated in the c/i-channel. the octat-p uses the t-channel to transmit the control channel information to the terminal. the t-channel is a subchannel of the u pn -interface with a bandwidth of 2 kbit/s. in the subscriber terminal the control channel is included again in the iom-2 interface. depending on the terminal configuration two alternatives can be selected in the terminal transceiver device. the blocked/available information is translated directly into the s/g-bit (stop/go) when no subsequent transceiver circuit is present in the terminal. the s/g-bit is evaluated by the terminal hdlc-controller icc. it stops data transmission immediately when the s/ g-bit is set to 1 (t-bit=0). when an additional transceiver device is integrated in the terminal (e.g. an s-adapter, peb 2081 (sbcx)) the control channel is translated into the a/b-bit. the a/b-bit is monitored by the sbcx. a/b = 1 indicates that the corresponding d-channel is available (a/b = 0 blocked). depending on this information, the sbcx controls the e-bit on the s-bus and the s/g-bit on the iom-2 interface. when a/b = 0 the e-bit is forced in the inverted d-bit state, the s/g-bit is set to high. as a result all active transmitters in the terminal and on the s-bus are forced to abandon their messages.
peb 2096 operational description data sheet 3-7 04.99 ? figure 3-5 control channel implementation with octat ? -p (peb 2096) as line card transceiver and s-adapter. line card mode -p isac te sbcx nt fsc iom -2 r dcl dd r pn u 2081 0 s peb te psb s/g a/b du 2196 kbit/s 384 m p iom -2 r 01 dcl elic t 0 iom lt fsc -2 r r sacco-b sacco-a d ch. arbiter control c/i peb r 2096 7 peb octat dd -p du c/i d kbit/s 2048 2345 8 b1 8 b2 8 mon 8 67 pcm 20550 p m d channel blocked d channel available 18 lf b1 0 4 8 b2 d 8 8 u pn b1 b2 1 1 mdc 1 11 cv ts 1 t = = 1 2 d 1100 = 1000 = mr 1 4 c/i 1 mx d channel available d channel blocked its07409
peb 2096 operational description data sheet 3-8 04.99 3.8 iom ? -2 interface monitor channel the monitor channel is used to convey message oriented information. this means that an information in the monitor channel is transferred once, and the receiver stores that message. there is a defined handshake procedure between the monitor channel transmitter and the receiver in order to ensure a safe data transfer over the iom-2 interface. the octat-p uses the monitor channel of iom channel 0 for local programming and reading (register access). the monitor channel operates on an asynchronous basis. while data transfer on the bus takes place synchronized to frame sync, the data flow is controlled by a handshake procedure using the monitor channel receive bit (mr) and the monitor channel transmit bit (mx). for example: data is placed onto the monitor channel and the mx bit is activated (active low). this data will be transmitted repeatedly once per 8 khz frame until the transfer is acknowledged via the mr bit. the monitor channel is in an idle condition when the mx bit is inactive in two or more consecutive frames (indication of end of message eom). before starting a transmission to the octat-p, the microprocessor should verify that the transmitter of the octat-p is inactive, i.e. that a previous transmission has been terminated. the octat-p has a monitor transmitter time-out function of minimum 4 ms implemented. this prevents the monitor message to be transmitted continuously if the monitor data wont be acknowledged by the receiver. an example for a m p, elic and octat-p communication is shown in figure 3-6 and figure 3-7. first the identification register of the octat-p may be read. two bytes are transmitted to the octat-p and as a result of the read operation two bytes are returned to the controller. in case of a write operation the data are only acknowledged and no data are returned from the octat-p to the controller. the first byte of the data transmitted to the octat-p always indicates the type of the desired monitor operation (i.e. read or write to the internal registers). the example shows the typical register access of the elic and gives a feeling about the important bits. the elic uses a 16-byte fifo for transmission and reception of the monitor data. therefore the user doesnt need to provide routines for the handshake protocol.
peb 2096 operational description data sheet 3-9 04.99 ? figure 3-6 monitor channel handling: m p ? elic ? octat-p
peb 2096 operational description data sheet 3-10 04.99 a detailed description of the hand-shake procedure using mx and mr bits is shown on figure 3-7. ? figure 3-7 monitor channel handling: hand-shake by the use of mx and mr bits
peb 2096 operational description data sheet 3-11 04.99 3.9 command / indicate channel the c/i channel is used for communication between the octat-p and a layer-2 device (or elic), to control and monitor layer-1 functions. the layer-2 device monitors the layer-1 indication continuously and indicates a change if a new code is found to be valid in two consecutive iom frames (double last look criterion). ? ? table 2 commands command (downstream) abbr. code remarks deactivate request dr 0000 reset res 0001 test mode 2 tm2 0010 transmission of pseudo-ternary pulses at 2 khz frequency test mode 1 tm1 0011 transmission of pseudo-ternary pulses at 192 khz frequency activate request = available ar 1000 transmission of info 2 or info 4, t bit set to one activate request test loop 2 ar2 1010 transmission of info 2, switching of loop 2 (at te), t bit set to one activate request local test loop arl 1001 transmission of info 2, switching of loop 1 (on u interface), t bit set to one activate indication = blocked ai 1100 transmission of info 4, t bit set to zero deactivate confirmation dc 1111 deactivation acknowledgment, quiescent state
peb 2096 operational description data sheet 3-12 04.99 in pbx applications with decentral d-channel handling, all d-channels can be handled by a d-channel arbiter of the elic, peb 20550; one signalling controller in multiplexer mode (sacco-a) can be used for up to 32 isdn subscribers. a terminal is allowed to send data only when the signalling controller is available and the subscriber was selected by the arbiter. the command c/i = 1000 b indicates to the octat-p that the selected d-channel can be used (is available), c/i = 1100 b indicates that the d-channel currently can not be used as the signalling controller is allocated to an other terminal. the addressed d-channel is blocked. the octat-p controls the terminal transmitter (e.g. isac-p te) accordingly. it translates the information whether the d-channel is available or blocked by setting the t-bit on the u pn interface. t = 1 indicates to the terminal (via the u pn transmitter) that its hdlc controller can send data. t = 0 indicates that the hdlc controller can not send data or has to abort sending data. note: the two codes (c/i = 1000 b and 1100 b ) can only be used when the octat-p is in a state info 4 transmission. table 3 indications indication (upstream) abbr. code remarks timing required (to activate iom-2) tim 0000 deactivated state, activation from the line not possible resynchronization (loss of framing) rsy 0100 receiver is not synchronous activate request ar 1000 info 1w received u only activation indication uai 0111 info 1 received synchronous receiver activate indication ai 1100 layer-1 fully activated deactivate indication di 1111 info 0 or dc received after deactivation request
peb 2096 operational description data sheet 3-13 04.99 3.10 activation and deactivation, state machine the activation and deactivation implemented in the peb 2096, octat-p, agree with the u p0 interface as implemented in the peb 2095, ibc. 3.10.1 states description octat-p state machine enters two different kind of states: unconditional and conditional states, figure 3-8.
peb 2096 operational description data sheet 3-14 04.99 ? figure 3-8 octat-p state diagram itd04467 activated al i4 i3 dc arx,al arx,al dc i1 i4 uai synchronized arx,al dc i1 i2 rsy resynchron. unconditional transitions initiated by commands: external pins: arx = ar, ar2, arl rst res, tm1, tm2 pend.act. ar i2 i1w dc arx deactivated di i0 i0 wait for dr di i0 i0 pend.deact. tim i0 i0 ind state cmd out in u dr i3 dr i3 i1 i1, i3 dc dr dr i1 i1w, arx dc dr dr dr arx tm2 tm1 * it tim test mode i dr tm1 tm2 reset tim i0 * res res dr dc i0 i xr i r iom i0 rst i3 *) refer to chapter chapter 2.2
peb 2096 operational description data sheet 3-15 04.99 unconditional states reset this state is entered unconditionally after a high appears on the rst pin or after the receipt of command res (software reset). the analog section is disabled (transmission of info 0) and the u pn interface awake detector is inactive. hence, activation from pt or te is not possible. test mode the test signal (it i ), sent to the u pn interface in this state is dependant on the command which originally invoked the state. tm2 causes single alternating pulses to be transmitted (it 2 ); tm1 causes continuous alternating pulses to be transmitted (it 1 ). the burst mode technique normally employed on the u interface is suspended in this state and the test signals are transmitted continuously. pending deactivation to access any of the conditional states from any of the above unconditional states the pending deactivation state must be entered. this occurs after the receipt of a dr command. in this state the awake detector is activated and the state is exited only when the line has settled (i.e. info 0 has been detected for 2 ms) or by the command dc. note: although dr is shown as a normal command it can in fact be seen as an unconditional command. no matter which state the lt is in, the reception of a dr command will always result in the pending deactivation state being entered. conditional states wait for dr this state is entered from the pending deactivation state once info 0 or dc has been identified. from here the line may be either activated, deactivated or a test loop may be entered. deactivated this is the power down state of the physical protocol. the awake detection is active and the device will respond to an info 1w (wake signal) by initiating activation.
peb 2096 operational description data sheet 3-16 04.99 pending activation this state results from a request for activation of the line, either from the terminal (info 1w) or from the layer-2 device (ar, ar2 or arl). info 2 is then transmitted and the octat-p waits for the responding info 1 from the remote device. synchronized upon receipt of info 1 the octat-p must synchronize itself to the signal. this process takes at most 10 ms. activated info 1 has a code violation in the framing bit (f bit) with respect to the last received bit whereas info 3 has none. upon the receipt of 2 frames without a code violation in the f bit, the octat-p enters the activated state and outputs info 4. the line is now activated; the octat-p sends info 4 to the remote, the remote sends info 3 to the octat-p. resynchronization if the octat-p fails to recognize info 3, for whatever reason, it will attempt to resynchronize. entering this state it will output info 2. this is similar to the original synchronization procedure in the pending activation state (the indication given to layer 2 is different). however as before, recognition of info 1 leads to the synchronized state. octat-p state diagram is shown in figure 3-8 . 3.10.2 info structure on the u pn interface signals controlling and indicating the internal state of all u pn transceiver state machines are called infos. four different infos (info 0, 1w, 1/2 and 3/4) can be sent over the u pn interface depending on the actual state (synchronized, activated, pending activation, test mode, deactivated, reset,...) of the connected transceivers (e.g. octat-p and isac-p te). when the line is deactivated info 0 is exchanged by the u pn transceivers at either end of the line. info 0 indicates that there is no signal on the line; in either direction. when the line is activated info 3 (in upstream direction) and info 4 (in downstream direction) are continually sent. info 3 and 4 contain the transmitted data (b1, b2, d, m).
peb 2096 operational description data sheet 3-17 04.99 info 1w and 1/2 are used for initialization and tests. the form of all info is shown in the following table: note: 1) the m channel superframe contains: cv code violation [1 kbit/s (once in every fourth frame)] s bits transparent [1 kbit/s channel] t bits set to one [2 kbit/s channel] 2) dc balancing bit f = framing bit name direction description info 0 upstream downstream no signal on the line info 1w upstream asynchronous wake signal 2 khz burst rate f0001000100010001000101010100010111111 code violation in the framing bit (f) info 1 upstream 4 khz burst rate f000100010001000100010101010001011111m 1) dc 2) code violation in the framing bit with respect to the last received 1 info 2 downstream 4 khz burst rate f000100010001000100010101010001011111m 1) code violation in the framing bit with respect to the last transmitted 1 info 3 upstream 4 khz burst rate no code violation in the framing bit user data in b, d and m channels b channels scrambled, dc bit 2) optional info 4 downstream 4 khz burst rate no code violation in the framing bit user data in b, d and m channels b channels scrambled, dc bit 2 ) optional
peb 2096 operational description data sheet 3-18 04.99 3.10.3 example of activation and deactivation an activation and deactivation procedure between an octat-p and an ibc or isac-p te in te mode over the u pn interface line is shown in figure 3-3 . it illustrates how the state machines of the respective modes interwork to facilitate activation and deactivation. in this case activation was initiated by an ar request at the terminal side and deactivation by a dr command at the lt side. activation could also be initialized at the lt side using an ar request. ? figure 3-9 example for an isac ? -p te <---> octat-p activation and deactivation note: t1: < 250 m s time for error free level detection t2: < 10 ms time for synchronization t3: 1 ms four subsequent bursts with no cv in f bit t4: 2 ms time for error free detection of info 0 info 0 ar lt info 2 uai info 4 info 1 info 1w info 0 info 0 di dr itd04468 t4 t2 t1 ai t3 info 3 te t1 info 0 t2 t3
peb 2096 registers description data sheet 4-1 04.99 4 registers description the monitor channel is used for programming local functions. it is implemented in octat-p iom channel 0 only. accesses to the registers are treated as local functions and therefore are marked with the code 1000 in the first four bits of the message: monitor message: register read an internal register is read by setting the internal address to zero (0 h ) and indicating the address of the specific register in the bits d(3:0). the bits d(7:4) are set to zero. e.g. 80 h 01 h is the read command for the register 1 h , the general configuration register. the response message from octat-p comprises two bytes, the first showing the address after the local-function-code, the second showing the register data. e.g. 81 h (d7:0) is the response to a read command on address 1 h , where d(7:0) is the content of the configuration register. register write an internal register is written by setting the internal address to the address of the specific register. the register will then be loaded with the value of d(7:0), e.g. 81 h 5d h programs the configuration register (addr. 1 h ) with the value 5d h . note: hardware reset or a corrupt iom frame (refer to chapter 2.2.2 ) leads to the initial value of all writable registers. 4.1 identification register C (read) address: 0 h value: 0 0 0 0 0 1 0 0 = 04 h description: the value of this register is specific for the peb 2096, octat-p. code = 1 0 0 0 internal address d7 d6 d5 d4 d3 d2 d1 d0 code = 1 0 0 0 0 0 0 0 0 0 0 0 register addr.= 01h code = 1 0 0 0 register addr. = 01h d7 d6 d5 d4 d3 d2 d1 d0 code = 1 0 0 0 register addr. 0 1 0 1 1 1 0 1
peb 2096 registers description data sheet 4-2 04.99 4.2 general configuration register C (write) address: 1 h format: initial value: ff h if the mode pin is connected to v dd or 01 h if the mode pin is connected to v ss description: icnd: iom interface channel n disable (channel 1-7) 0...iom channel n is enabled 1...iom channel n is tristated bem: bit error mask 0...whenever the bit error register value is unequal to zero, the register value is transmitted via the monitor channel 1...the bit error register may be read, but there are no unsolicited monitor messages 4.3 bit error register C (read) address: 1 h format: initial value: 00 h description: beon = 1: bit error occurred on u pn line n. the bit error register is reset after reading the register 4.4 test registers C (read/write) test registers are implemented in the address range of 8 h to b h ; they are not for customer use. bit 7 bit 0 ic7d ic6d ic5d ic4d ic3d ic2d ic1d bem bit 7 bit 0 beo7 beo6 beo5 beo4 beo3 beo2 beo1 beo0
peb 2096 registers description data sheet 4-3 04.99 4.5 line delay measurement of the u pn interface the delay of each u pn interface cable can be measured by one 8-bit counter with a programmable resolution of 65 ns or 130 ns. the line delay time w g can be measured in the range up to 16.57 m sec with the resolution of 65 ns and 33.15 m sec with the resolution of 130 ns . ? the access to the delay measurement control logic is done via the iom-2 monitor chan- nel of iom-channel 0. &rqiljxudwlrq5hjlvwhuiru8 31 /lqh,qwhuidfhv:ulwh address: 2 h format: initial value: 00 h if the mode pin is connected to v dd or 20 h if the mode pin is connected to v ss description: '6(/ selects the u pn line interface of which the delay measurement is executed 0 h : u pn transceiver no. 0 is selected 1 h : u pn transceiver no. 1 is selected 2 h : u pn transceiver no. 2 is selected 3 h : u pn transceiver no. 3 is selected bit7 bit0 synen balen equdis tod '6(/ '6(/ '6(/ 5(62/
peb 2096 registers description data sheet 4-4 04.99 4 h : u pn transceiver no. 4 is selected 5 h : u pn transceiver no. 5 is selected 6 h : u pn transceiver no. 6 is selected 7 h : u pn transceiver no. 7 is selected 5(62/ resolution of the delay counter for the u pn interface 0: resolution of 65 ns 1: resolution of 130 ns 72' time out disable 0: enable (after reset) 1: disable
peb 2096 registers description data sheet 4-5 04.99 'hod\5hjlvwhuiru8 31 /lqh,qwhuidfhv5hdg address: 2 h format: initial value: 00 h '(/$< measured delay between u pn transmit and receive frame with a programmed resolution of 65 ns or 130 ns. the measured value indicates the delay between the transmitted m bit and the received lf bit minus two bits (the guard time). in order to evaluate the delay in one direction the measured delay is divided by two. after hardware reset, the line delay of transceiver no. 0 is measured with a resolution of 1 oscillator period. the delay is measured only if the selected channel is in the state "activated". the measured delay is valid if at least 2 u pn frames have been received in the state "activated". if the selcted transceiver no. was changed by programming the configuration register for u pn line interfaces with a new value the new delay is also valid after the receiption of at least 2 u pn frames. the transmitter and receiver delays of octat-p analog path are included in the delay measurement. bit7 bit0 delay7 delay6 delay5 delay4 delay3 delay2 delay1 delay0
peb 2096 electrical characteristics data sheet 5-1 04.99 5 electrical characteristics note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. line overload protection the maximum input current (under voltage conditions) is given as a function of the width of a rectangular input current pulse. for the destruction current limits refer to figure 5-1 . ? figure 5-1 5.1 absolute maximum ratings t a = 0 to 70 c; v dd = 5 v 5 %; v ss = 0 v parameter symbol limit values unit ambient temperature under bias: peb t a 0 to 70 c storage temperature t stg - 65 to 125 c voltage on any pin with respect to ground v s - 0.4 to v dd + 0.4 v maximum voltage on any pin v max 6v
peb 2096 electrical characteristics data sheet 5-2 04.99 ? figure 5-2 maximum line input current 5.2 dc characteristics t a = 0 to 70 c; v dd = 5 v 5 %, v ss = 0 v all pins except lina,b; xtal1, 2 parameter symbol limit values unit test condition min. max. l-input voltage v il C 0.4 + 1.5 v h-input voltage v ih 2.0 v dd + 0.4 v l-output voltage v ol v ol1 0.45 0.45 v v i ol = 2 ma i ol = 7 ma (du only) h-output voltage v oh 2.4 v i oh = C 400 m a h-output voltage v oh v dd C 0.5 v i oh = C 100 m a input leakage current i li i lo 1 m a0 v v in v dd 0 v v out v dd all pins except: lina, b; xtal1,2; tdi; tms tdi; tms
peb 2096 electrical characteristics data sheet 5-3 04.99 input leakage current high i lih 1 m a v in = v dd input leakage current low i lil 50 400 m a v in = 0 v; internal pull-up resistor lina, b operational supply current i cc 50 + n 2.8 ma v dd = 5 v inputs at v ss / v dd , transformer ratio 2:1 n = number of line interfaces activated, no output load at clk, du transmitter output impedance 730 w i out = 20 ma v dd = 5 v receiver input impedance z r 10 k w v dd = 5 v; transmitter stage inactive xtal1 h-input voltage v ih 3.5 v dd + 0.4 v l-input voltage v il C 0.4 1.5 v xtal2 h-output voltage v oh v dd - 0.5 v i oh = 100 m a, c ld 60 pf l-output voltage v ol 0.45 v i ol = 100 m a, c ld 60 pf 5.2 dc characteristics (contd) t a = 0 to 70 c; v dd = 5 v 5 %, v ss = 0 v all pins except lina,b; xtal1, 2 parameter symbol limit values unit test condition min. max.
peb 2096 electrical characteristics data sheet 5-4 04.99 ? figure 5-3 recommended oscillator circuits 5.3 capacitances t a = 25 c; v dd = 5 v 5 %, v ss = 0 v all pins except lina, b parameter symbol limit values unit test condition min. max. pin capacitance c i/o 7pf lina,b output capacitance against v ss c out 10 pf xtal1, 2 recommended typical crystal parameters. refer to figure 3-5. motional capacitance c 1 20 ff shunt c 0 7pf load c l 30 pf resonance resistor r r 65 w its07328 15.36 mhz xtal 1 2 xtal xtal 2 1 xtal n.c. oscillator external signal crystal oscillator mode driving from external source 100 ppm c ld ld c c ld =2 . l c - c i/o minimum high time : 24 ns minimum low time : 24 ns
peb 2096 electrical characteristics data sheet 5-5 04.99 5.4 ac characteristics t a = 0 to 70 c; v dd = 5 v 5% ac testing: inputs except xtal1 are driven at 2.4 v for a logic 1 and at 0.4 v for a logic 0. xtal1 is driven at v dd - 0.5 v for a logic 1 and 0.5 v for a logic 0. timing measurements are made at 2.0 v for a logic 1 and at 0.8 v for a logic 0. ? figure 5-4 jitter the clock input fsc is used as reference clock to provide the 768 khz clock for the u pn interface. in the case of a plesiochronous 15.36 mhz clock generated by an oscillator with a maximum frequency deviation of 100 ppm, the clock fsc should have a jitter of less than 20 ns peak-to-peak, as the pll manages max. 0.5 oscillator period (32.5 ns) in one iom frame (in 125 m s). its07329 = 100 load c test under device 0.5 2.0 0.8 0.8 2.0 test points pf v dd v - v 0.5 ttl input level for all inputs exept xtal1 ttl output level cmos input level for xtal1
peb 2096 electrical characteristics data sheet 5-6 04.99 5.5 clocks clk1 clk2 clk2 is directly derived from the oscillator clock and can drive up to 6 oscillator inputs of the isac-s, peb 2085. ? figure 5-5 definition of clock period and width parameter symbol limit values unit test condition min. max. high phase of crystal/clock t wh 25 ns 50 pf load capacitance at clk low phase of crystal/clock t wl 25 ns 50 pf load capacitance at clk clock period t p 65.08 65.12 ns parameter symbol limit values unit test condition min. max. high phase of crystal/clock t wh 57 ns 50 pf load capacitance at clk low phase of crystal/clock t wl 57 ns 50 pf load capacitance at clk clock period t p 130.16 130.24 ns itt00766 3.5 v 0.8 v t wh t p t wl
peb 2096 electrical characteristics data sheet 5-7 04.99 5.6 timing of the iom ? interface ? figure 5-6 iom ? interface timing with double data rate dcl
peb 2096 electrical characteristics data sheet 5-8 04.99 ? parameter symbol limit values unit min. max. frame sync. hold t fh 30 ns frame sync. setup t fs 70 ns frame sync. high t fwh 130 ns frame sync. low t fwl t dcl data delay to clock t ddc 100 ns data setup t ds 20 ns data hold t dh 50 ns superframe sync. setup t ssys 200 ns superframe sync. hold t ssyh 200 ns data clock high t dwh 50 ns data clock low t dwl 50 ns
peb 2096 electrical characteristics data sheet 5-9 04.99 ? figure 5-7 iom ? -2 interface timing with single data rate dcl
peb 2096 electrical characteristics data sheet 5-10 04.99 ? figure 5-8 ssync timing note: a low at ssync input sets the u pn superframe and forces the next transmitted t-bit to high if synen is programmed to high. 5.7 boundary scan timing ? parameter symbol limit values unit min. max. test clock period t tcp 160 ns test clock period low t tcpl 80 ns test clock period high t tcph 80 ns tms setup time to tck t mss 30 ns tms hold time from tck t msh 30 ns tdi setup time to tck t dis 10 ns tdi hold time from tck t dih 30 ns tdo valid delay from tck t dod 70 ns
peb 2096 electrical characteristics data sheet 5-11 04.99 ? figure 5-9 boundary scan timing
peb 2096 electrical characteristics data sheet 5-12 04.99 5.8 u pn frame relation to fsc in transmit direction the lf-bit on the u pn interface appears t0 after the last but two (3 rd last falling edge) falling edge of dcl before fsc rising edge ( figure 5-10 ). ? figure 5-10 f-bit delay to fsc in double clock mode itd07417 ~ ~ fsc dcl llna, b f-bit t 0 ~ ~ ~ ~
peb 2096 electrical characteristics data sheet 5-13 04.99 figure 5-11 f-bit delay to fsc in single clock mode t0 = 85 oscillator periods + analog delay 0.5 oscillator periods analog delay < 1 oscillator period (15.36 mhz) itd11109 ~ ~ fsc dcl llna, b f-bit t 0 ~ ~ ~ ~
peb 2096 electrical characteristics data sheet 5-14 04.99 5.9 transceiver characteristics a detailed transceiver architecture is shown in figure 5-12 . it comprises the transmitter output stages, the differential-to-single ended receiver input stage, the loop switch, the peak detector, and the threshold comparators. ? figure 5-12 detailed transceiver architecture when transmitting a binary one, the transmitter output is 5 v (difference between lina and linb), when transmitting a binary zero, the transmitter output is in tristate. the receiver input range is from 5 v to 150 mv. the 150 mv level is a fixed minimum peak level.
peb 2096 electrical characteristics data sheet 5-15 04.99 power supply rejection ratio (psrr) the psrr of the receiver is better than C 40 db at frequencies below 100 khz, decreasing by 20 db per decade above 100 khz. noise immunity the noise immunity target of the receiver is better than 10 m v/ ? hz in the range up to 1 mhz, which should be achieved by both adaptive thresholds and digital oversampling techniques. crosstalk immunity the receiver immunity against crosstalk between neighbor receive channels, measured with minimum and maximum input levels at two neighbor inputs should not effect the overall transceiver performance according to the u p0 specification.
peb 2096 package outlines data sheet 6-1 04.99 6 package outlines ? p-mqfp-44 (plastic metric quad flat package) gpm05622 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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